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Who wrote this stuff?
This trivia was originally written by Jim Brain as part of the now long defunct C= Hacking Magazine, but happily Jim has kindly agreed to let me reproduce it in HTML-ized format for retro computing fans everywhere.

If you are interested in seeing the Commodore Trivia digests in their original form, take a look at this website.

For those who are interested, these pages were generated from the original text files using Perl and Velocity (and a nice template originally found here)


	The 6502 has a rich history.  It is modeled after another 8-bit
        microprocessor.  Name the processor.

	The 65XX series of processors was modeled after the Motorola 6800.
        Motorola hampered the design groups' efforts to pursue product
        developments using the 6800.  A core group of 8 designers left Motorola
        and went to MOS Technologies, which was the largest producer of
        calculator chips at the time.  MOS decided it was time to go into
        the CPU business.

	The 6502 has a older brother that was never produced.  Name its
        number designation and why it was not produced.

	The older brother to the 6502 was the 6501.  The 6501 was
        pin-compatible with the 6800, which prompted a suit by Motorola.
        Eventually, MOS reached an agreement where they scrapped the 6501
        marketing, but were free to market the 6502.

	How many different opcodes are considered valid and "legal" on the
        MOS NMOS 6502 line?

	151 opcodes are documented in the NMOS 6502 data book.  The remaining
        105 opcodes were not implemented, and exist as "don't care" states
        in the opcode matrix.  That means that some seemingly invalid
        opcodes will actually perform pieces of two or more valid opcodes.
        Newer CPU systems trap all non-implemented opcode usages, but not
        the 6502.

	Every instruction takes at least __ cycles to complete.  Fill in
        the missing number.

	2.  The architecture assumes that each opcode has two bytes in it and
        one byte can be fetched per cycle.  For instructions that use only
        1 byte, the extra fetched byte (actually the next opcode), is thrown

	Which instructions take more time than necessary as a result of the
        answer to Q $093?

	Although this is a subjective answer, One could nominate NOP on the
        basis that NOP is generally believed to waste one execution cycle on
        a particular processor, namely one cycle on the 65XX line.  However,
        one can argue that NOP simply means no operation, and has no ties to
        length of execution.  You be the judge.
        All other instructions must take at least two cycles: one for opcode
        fetch, one for operation.

	What did MOS Technologies manufacture befor introducing the 650X line
        of microprocessors?

	As stated above, it was calculator chips.

	Three companies manufactured the 6502 under a cross-licensing
        agreement.  Name them.

	Rockwell, MOS Technologies, and Synertek.

	In NTSC-land, how fast does the 1MHz 6510 in the C64 actually run?

	1.022727143 MHz.  It is derived by taking the main clock frequency
        (14.31818MHz) and diving it by 14.

	What about in PAL-land?

	985.248449 kHz.  It is derived by taking the main clock frequency
        (17.734472MHz) and dividing it by 18.  Thus the PAL 64 actually runs
        slower than the NTSC one.

	Data is latched into the 650X microprocessor on the (rising/falling)

	Data is latched in to the 65XX on the falling edge of Phi0 (Phi1).
        The timing diagram in some books (64 PRG is one) is incorrect.

	Through the years, the 650X line has changed family numbers, yet
        the part has not been changed.  (A family number is the upper 2
        digits in this case)  Name the other family numbers used by MOS to
        denote the 650X line.

	the 75XX line used in the 264 series (Plus/4 and C16), and the 85XX
        series used in the C64C and C128 series.

	Consider the following code:
        ldx #10
        lda $ff,x
        what location does the accumulator get loaded with?

	The answer is location $ff+10 mod 256 = $09.
        The answer involves explaining a (mis)features of the NMOS 65XX CPU
        line.  The above code instructs the 65XX CPU to use zero-page 
        addressing mode to load the accumulator.  In zero-page addressing, the
        address need only be one byte wide ($ff in this case), because the
        high byte is considered to be $00.  Now, as humans, we would expect
        the CPU would add 10 to 255 ($ff), giving 265 ($109) as the address
        to load the accumulator from.  However, the CPU designers decided 
        that zero-page addressing means that the high byte will be $00 all the
        time, no exceptions.  If a situation like the above occurs, the 
        low byte of the addition will be used as the low byte of the address
        (9 in this case), but the high-byte will be ZERO.  All zero page
        addressing modes work this way.  Note that the CMOS versions of the 
        6502 do perform the high byte "fix-up", so this behavior is only seen
        on the NMOS parts.

	What about the following?
          ldx #10
          lda ($ff),x

	This was a trick.  The code is trying to use INDIRECT INDEXED indexing
        mode using the x register, but that addressing mode can only be used
        with the y register.  If the code is changed to the following, legal
          ldx #10
          lda ($ff),y
        Then, the above discussion for zero-page addressing holds true here 
        as well.  The effective address would have been (hi:lo) $100:$0ff, but
        is instead (hi:lo) $000:$0ff.  The simple rule is:  zero page means
        exactly that.  There is no way to address outside of zero-page with
        zero-page addressing.

	How many CPU clock signal lines does the 650X require to run?

	1.  The 6501 used two, as the 6800 used two, but the 6502 and
        successors only required Phi0 (Phi1).  Phi2 was generated on the CPU.

	Where does the 650X line fetch its first byte from after reset?

	$fffc.  The address formed by reading $fffd and $fffc is stuffed into
        the IP, and the code is read starting there.  $fffc is read first,
        since the 65XX line stores addresses in low byte, high byte format.

	One of the original designers on the NMOS 6502 CPU now heads up
        Western Design Center in Arizona, and makes the 65C02 and 65C816
        CPU chips.  Name him.  Hint: it is not Chuck Peddle!

	Bill Mensch.  He hand-designed these newer parts in the 65XX line
        in the same manner he and Chuck Peddle and others hand-designed the
        6501 and 6502.

Jim Brain
10710 Bruhn Avenue
Bennington, NE  68007
(402) 431-7754


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